Cadence Subsystem for PCIe 6.0 Architecture Achieves First-Pass PCI Express Specification Compliance
Complete x8 subsystem solution in TSMC N3 process demonstrates industry readiness for mass production and de-risks adoption for AI/HPC customers Cadence (Nasdaq: CDNS) today announced that its PHY and controller IP for the PCI Express® (PCIe®) 6.0 specification, implemented in the TSMC N3 process,…
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